Simple Interval Temporal Logic for Natural Language Assertion Descriptions

SystemVerilog assertion (SVA) is widely used for verifying properties of hardware designs. This paper presents a new method of generating SVAs from natural language assertion descriptions. For capturing the temporal semantics in natural language descriptions, we develop a new logical form called simple interval temporal logic (SIT L) which can deal formally with temporal constructions such as temporal prepositions. Furthermore, SIT Lmakes the transformations from natural language descriptions to SVAs possible. Thus, we build transformation rules to map our logic into SVAs. Our systematic experimental investigation on AXI bus protocol in ARM (2010) suggest that our method is applicable for generating SVAs from natural language descriptions.